1. Field of the Invention
The present invention relates to a semiconductor device in which a bipolar transistor is provided, such as a BiCMOS, and a production process thereof, more specifically relates to a bipolar type semiconductor device having a small parasitic capacitance, excellent voltage resistance, the minimum dimensions and little variation in the transistor characteristic and to a production process thereof.
2. Description of the Related Art
For example, as disclosed in Denshi Joho Gakkaishi C-II (issued in November 1990, vol. J73-C-11, No. 11, page 759 to 766), a higher speed operation of an ultra-high speed bipolar transistor depends on how the parasitic capacitance can be reduced by wielding self-alignment technology. The construction of the bipolar transistor disclosed in this document adopts an OSET (outside emitter technology), in which a base contact region is provided at the center and an annular emitter region is provided at the outside thereof. By adopting this construction, irrespective of the miniaturization of the element, it becomes possible to relatively increase the surface area of the emitter region and, at the same time, to relatively reduce the base region. An increase of density by the reduction of the dimensions of the elements becomes possible simultaneously with the reduction of the parasitic capacitance. However, the technology disclosed in this document has a problem in that the production process becomes very complex.
Also, as a construction of the bipolar transistor which achieves a reduction of the parasitic capacitance and achieves an improvement of the speed, as shown in FIG. 48, there is adopted a construction in which an epitaxial layer 6 is deposited on the surface of a semiconductor substrate 4 in which a collector burying layer 2 is provided, a trench type isolation region 8 is formed on the surface of this epitaxial layer 6, and a graft base 10 is formed adjacent to this trench type isolation region 8. Note that, in the figure, reference numeral 12 denotes an intrinsic base region; 14, an emitter region, and 16, a base electrode.
In a bipolar transistor in which such a trench type isolation region 8 is provided, there is the effect that the parasitic capacitance between the collector and base is reduced in accordance with the portion where the graft base 10 and the isolation region 8 are in contact with each other.
The illustrated bipolar transistor also has a problem, however, in that the production process thereof are complex. Also, in this transistor, a matching margin of the base electrode must be ensured with respect to the trench type isolation region 8, and therefore the element becomes big in size and thus is not suitable for high density. Moreover, when it comes to the positional relationship between the trench type isolation region 8 and the emitter region 14, since the process is not a production process which is determined by self-alignment, there is a problem in that the characteristic of the bipolar transistor (for example the cut-off frequency f.sub.T) varies.
Note that, Japanese Unexamined Patent Publication (Kokai) No. 63-244768 discloses a technology for forming the graft base by self-alignment with respect to the emitter electrode. By this technology, an improvement of the characteristics, for example, the reduction of the base resistance, can be expected, but this technology cannot reduce the parasitic capacitance between the emitter and base.